Frequency converter for the stabilized power supply of asynchronous motors

ABSTRACT

A frequency converter is provided for the power supply of an asychronous motor, comprising: 
     a rectifier bridge (11) connected to a multiphase network and to an intermediate DC circuit (12); 
     an inverter (13) comprising three pairs of static switches (T1-T6) connected in a Graetz bridge; characterized by; 
     a means (21) for reading the current associated with the intermediate circuit (12) and elaborating an image signal of the reverse circuit and delivering an image signal of the current in this circuit; 
     a stabilization control circuit (22) connected to said means (21) and delivering a reverse current excess signal (ST) when the signal (I d ) exceeds an adjustable threshold; and 
     a means (25) for reducing the output voltages of the inverter, and adapted for modifying the modulated pulses, this means being controlled by the output signal (ST) of the stabilization control circuit (22).

The invention relates to a static frequency converter for the powersupply of an asynchronous type motor, including a rectifier bridgeconnectable to a multiphase network, an intermediate DC circuit and aninverter with six static switches connected in a Graetz bridge,controlled by a pulse modulation device and connectable to the phaseimpedances of the motor.

Asynchronous motors fed from three-phase networks through frequencyconverters generally suffer from operating instability when they arelightly loaded. The appearance of an oscillation of the rotor of themotor may in fact be observed due to an energy exchange between themotor and the intermediate DC circuit in a frequency range of about 20to 100% of the nominal frequency.

For correcting such instability, it would be possible to use a speedservo-control using a speed sensor, or else current sensors in the phaseconductors of the motor, but such solutions are expensive andnecessarily associated with the motor.

As is known, the voltage U and the frequency F for the supply of anasynchronous motor through a frequency converter must remain normallyrelated by a given law, for example with a constant U/F ratio.

The aim of the present invention is especially to overcome the lowfrequency oscillation of the rotor of a lightly loaded asynchronousmotor by reducing the power supply voltage U of the motor when such anoscillation occurs so as to momentarily reduce the U/F ratio. It aims inaddition at stabilizing the drive of the motor using a simple device,while providing a good compromise between the drive quality and thedesired stability.

It has as object to combine the desired low load stabilization with alimitation of the currents of the motor at the time of sudden loadvariations.

In accordance with the invention, the frequency converter includes ameans for reading the current associated with the intermediate DCcircuit and delivering a signal which is the image of the current in theintermediate circuit, processing means connected to the reading meansand adapted for detecting instability of the signal, and a means forreducing the output voltages of the inverter, this means being adaptedfor modifying the modulated pulses delivered by the control device andbeing controlled by the processing means.

The frequency deviation thus obtained reduces the U/F ratio and placesoperation outside the zone of instability.

The means for reducing the output voltages of the inverter may cooperatewith the device controlling the static switches of the inverter foralternately disabling the high channel switches and the group of lowchannel switches synchronously with the modulation exerted on each groupof switches. The result is a good symmetrization of the currents of themotor.

In a first embodiment, the processing means deliver a reverse currentexcess signal ST and include a processing circuit connected to thecurrent reading means and elaborating a filtered peak signal I_(d)representative of the peak value of the reverse current and a comparatorcomparing this signal with an adjustable reference value I_(REF) forgenerating, when I_(d) >I_(REF), the reverse current excess signal STapplicable to the output voltage reduction means.

The construction of the stabilization device is thus very simple.Furthermore, it facilitates the addition of simple means for inhibitingthe signal ST when the motor operates as a generator and, when required,disabling of the high or low channel or alternately of the high channeland of the low channel switches when a high load surge is detected inthe generator mode.

In a second embodiment, the processing means include a memberestablishing the mean value of the image signal of the current in theintermediate circuit, as well as an A-D converter receiving the meanvalue signal and delivering a digital signal; the voltage reductionmeans include a processor having means for sampling the digital signaland means for evaluating the amplitude and/or the oscillation frequencyof the signal; the control device includes modulation control means formodulating the conduction of the switches, the oscillation evaluationmeans acting on the modulation control means for correcting saidmodulation as a function of the oscillation of the mean current in theintermediate circuit. The voltage reduction means and the control devicemay advantageously be implemented in a suitably programmedmicroprocessor.

The following description with reference to the drawings of a particularembodiment will clearly show the characteristics and advantages of theinvention.

In the accompanying drawings:

FIG. 1 is the diagram of a static frequency converter in accordance withthe invention;

FIG. 2 shows a part of the diagram of FIG. 1 in a first embodiment;

FIGS. 2A, 2B, 2C are timing diagrams showing respectively the imagesignals of the current in the intermediate circuit, of its reversecurrent component and the stabilization control signal;

FIG. 3 shows a timing diagram of an output phase voltage of the inverterof the converter of FIG. 1;

FIG. 4 shows one example of routing the current in the low channels ofthe inverter when the high channels thereof are disabled;

FIG. 5 shows schematically one embodiment of the stabilization circuitassociated with the inverter;

FIG. 6 shows schematically a second embodiment of the frequencyconverter of the invention.

The static frequency converter 10 illustrated in FIG. 1 is connected toa three-phase or possibly single-phase AC voltage network. The converteris of the voltage wave type and includes a three-phase rectifier bridge11, an intermediate DC circuit 12 and an inverter 13. The rectifierbridge 11 has six diodes connected to the phases of the network so as tooutput a DC voltage to the intermediate circuit 12. This latter includestwo respective high channel and low channel conductors 14, 15 betweenwhich is disposed a filtering capacitor 16. The polarity at theterminals of capacitor 16 remains constant.

The inverter 13 is connected, on the input side, to conductors 14, 15and, on the output side to the phase conductors U, V, W of anasynchronous motor M. The motor could also be a synchronizedasynchronous motor.

The inverter includes six controlled static switches connected in aGraetz bridge and formed, in the present embodiment, by three pairs ofbipolar transistors T1-T6 in parallel with which are disposed respectiverecovery diodes D1-D6. Each pair of transistors includes two cascadedtransistors T1, T2; T3, T4; T5, T6 one of which T1, T3, T5 is said to behigh channel and the other T2, T4, T6 low channel. The middle point ofeach pair is connected to a respective stator impedance ZU, ZV, ZW ofthe motor (see FIG. 4). The controlled switches of the inverter may bedisablable (GTO) or non disablable (SCR) thyristors with assistedswitching if required or else isolated grid transistors, or MOS bipolarcomponents.

The bases of the high channel transistors T1, T3, T5 are controlled viarespective conductors 20H by the outputs S1, S3, S5 of a control device20. The bases of the low channel transistors T2, T4, T6 are controlledvia conductors 20B by the outputs S2, S4, S6 of device 20. This deviceis, for example, a microprocessor adapted for generating at its outputsthe modulated width pulses (PWM) required for driving the bases of thetransistors as a function of the information delivered to the inputs ofthe microprocessor by regulation or control loops not shown.

In accordance with the invention, a means 21 is provided for reading thecurrent in the intermediate circuit 12. This means delivers a signal Iwhich is the image of the current and it is connected to a processingmeans 22 which, in the example of FIG. 2, elaborate a filtered peaksignal I_(d) which is the image of the reverse current and whichgenerates a stabilization control signal ST representative of an excessreverse current. Means 21 sensors the current in conductor 15, but itcould of course be associated with conductor 14. The current readingmeans 21, is here formed by a resistor, but may be any appropriatecurrent sensor.

The processing means 22 are connected to a means 25 for reducing theoutput voltage of the inverter. In the example shown in FIG. 2, theprocessing means 22 include a processing circuit 23 which delivers thesignal I_(d) which is the image of the reverse current and a comparator24. The processing circuit 23 extracts from the signal I delivered bymeans 21 the component I_(d) representative of the reverse current i_(d)generated by the inverter particularly during oscillations of the motor.This reverse current may also be called "diode" current since it passesthrough the recovery diodes of the inverter.

Comparator 24 compares the signal I_(d), image of the reverse current,with a reference value I_(REF) for producing the stabilization controlsignal ST when I_(d) >I_(REF). The reference value I_(REF) is preferablyadjustable so more particularly as to allow the stabilization to beadapted to the motor fed by the frequency converter and/or to the drivenload.

The stabilization control signal ST obtained at the output of comparator24 is applied to the means 25 for reducing the output voltages of theinverter. This reduction means is here formed by a logic circuit orstatic switches blocking, during the change of state of the output ST ofthe comparator, the pulses normally delivered by the outputs S1, S3, S5of the microprocessor associated with the high channels of the inverter.The logic circuit 25 could of course as a variant block the outputs S2,S4, S6 corresponding to the low channels of the inverter. When thestatic switches of the inverter are disablable thyristors (GTO), thelogic circuit 25 may also control the forcing of turnoff conductors ofthe GTOs.

The signals I, I_(d) and ST are illustrated in FIGS. 2A, 2B and 2Cwhereas the shape of the chopped voltage Vs appearing at the output ofthe inverter on one phase is shown in FIG. 3; the routing of the currentflowing during blocking of the high channels is illustrated in FIG. 4.

The voltage Vs is formed of alternately positive and negative groups ofpulses P of variable width (FIG. 3). Each pulse corresponds to thesimultaneous enabled state, under the effect of the correspondingsignals on conductors 20H, 20B of a high channel transistor and of a lowchannel transistor. These pulses P are separated by intervals C ofvariable width. When an operating instability occurs, for examplebecause the asynchronous motor is lightly loaded, the current in theintermediate circuit assumes the trend shown in FIG. 2A. The positivepart of the signal I is a signal which is the image of the motor currentor of the current in the transistors, the negative part of the signal Ibeing the image signal of the reverse current or "diode" current. Theprocessing circuit 23 extracts from I the filtered peak signal I_(d)which is compared with I_(REF) (FIG. 2B) in the comparator 24, thislatter delivering at its output the signal ST (FIG. 2C).

The means 25 which on the one hand receives the signal ST and on theother the signals S1, S3, S5 provides a succession of brief turn-offs ofthe whole of the high channel transistors of the inverter; the result isan additional chopping of the voltage Vs by intervals C' formed in thepulses P.

In FIGS. 4, it has been assumed that the high channel transistors T1,T3, T5 are disabled by appropriate signals on conductors 20H and thesignals on conductors 20B have just controlled the closure of T4 and thedisabling of T2 and T6. It can be seen that the current flows betweentransistor T4 and the antiparallel recovery diodes D2 and D6. Thebetween phase voltage is zero. More generally, in the case of disablingof one of the groups of channels of the inverter, the path of thecirculating current is looped to one of the transistors and to therecovery diodes associated with the other two transistors of the othergroup of channels.

In the embodiment shown in FIG. 5, the signal delivered by the currentreading means 21 is amplified by an amplifier 26 then processed in threecontrol channels 27, 28, 29.

The control channel 27 includes an amplifier-comparator 30 whichreceives the signal I at an inverter input, for revealing the negativecomponent of signal I, as well as filtering and peak detection of thiscomponent so as to provide the signal I_(d), the image of the envelopeof the reverse current. Comparator 30 compares the signal I_(d) with anadjustable reference signal I_(REF), obtained from a fixed voltageV_(REF) by means of an adjustment potentiometer 31 and it generates anoutput signal ST when I_(d) >I_(REF).

The control channel 28 includes an amplifier-comparator 32 providingfiltering and peak detection of the image signal of the transistorcurrent I_(t) and comparison thereof with a fixed threshold, as afunction of a voltage V_(REF). The signal ST' resulting fromovershooting of the threshold by signal I_(t) is applied to an input ofan OR gate 33 whose other input receives the signal ST. The outputsignal of the OR gate 33 transits through a delay element 34 forapplication for a given time by this element to the first inputs of ANDgates 35, 36, 37 forming the disabling means ensuring the desiredvoltage reduction. Second inputs of the AND gates 35, 36, 37 receiverespectively the signals S1, S3, S5. The delay element is a rapid chargeand slow discharge RC circuit but may also be formed by a monostableflip-flop; it avoids imposing too high a chopping frequency on thetransistors.

The control channel 29 has a means 38, for example an integrator orsimilar means, providing the mean value I_(d) of the image signal of thereverse current I_(d) and emitting a signal G for inhibiting the signalST when this mean value exceeds a given threshold. The signal G is forexample fed to the amplifier-comparator 30. Thus, when the motor isoperating as a generator, the signal G inhibits the appearance of signalST and thus prevents disabling of the transistors T1, T3, T5 of the highchannels. The comparators described may be threshold operators.

The frequency converter described operates in the following way: duringnormal operation of the motor, the current flows through line 15 of theintermediate circuit 12, as shown by arrow i_(t) in FIG. 1. The controlcircuit remains inactive.

Should oscillation or instability occur due to a low load of the motor,a reverse component appears as is indicated by the arrow i_(d) inFIG. 1. The processing circuit 23 develops then the signal I_(d) and thecomparator 24 - or the amplifier 30 which combines the functions of 23and 24 - generates a succession of pulses forming the signal ST. Thesepulses disable the gates 35-37 and the result is additional chopping C'of the modulated width pulses P delivered by the control device 20 untilthe detected instability disappears.

When the motor is operating as a generator, the signal I_(d) of the meanvalue of current i_(d) reaches a sufficient value for the signal G' tochange state and lock the comparator 30, so that the reverse current mayflow normally to the three-phase network.

When a high load variation is detected by channel 28, the signal ST'changes state and the high channels of the inverter are disabled, as inthe above mentioned case of too low a load.

As is known, in a frequency converter of the type described, the controldevice 20 produces an alternate modulation of the conduction of theswitches of the first group T1, T3, T5, then of the second group T2, T4,T6, then again of the first group T1, T3, T5, etc. . . , the groups ofconductors 20H, 20B being thus activated alternately.

Preferably, the output voltage reduction means 25 will deliver voltagereduction intervals C' also alternately to the groups of modulatingswitches, that is to say synchronously with the modulation provided bythe groups of conductors 20H, then 20B, etc...Thus, the currents of themotor are symmetrized and the troublesome effects of parasite diodecurrents are reduced.

The output voltage reduction means 25 and possibly a part of theprocessing means 22 are implemented in the same control logic, forexample in the same microprocessor.

In the embodiment shown in FIG. 6, the processing means 22 include ameans 40 providing the means value I_(m) of the image signal I of thecurrent in the intermediate circuit, as well as an A-D converter 41receiving the mean value signal I_(m) and delivering a digital signalI_(mn).

The voltage reduction means 25 include a processor having means forsampling the digital signal I_(mn) and means for evaluating theamplitude and/or the frequency of oscillation of the signal I_(mn).

The control device 20 is a microprocessor which includes the voltagereduction means 25. Microprocessor 20 has modulation control means formodulating the conduction of switches T1-T6; the oscillation evaluationmeans interact on the modulation control means for correcting themodulation as a function of the evaluated value of the oscillation ofthe mean current in the intermediate circuit. The means included inmicroprocessor 20 are in material and software form.

I claim:
 1. A frequency converter for an AC power supply of anasynchronous type motor, comprising:i. a rectifier bridge having inputAC terminals which can be connected to a multiphase network and two DCoutput terminals connected to two respective conductors of a DCintermediate circuit; ii. an inverter having two DC input terminalsrespectively connected to the said conductors so as to receive a DCcurrent provided by the rectifier and flowing in the conductors, saidinverter comprising three pairs of static switches, each pair beingconnected to the two DC input terminals and comprising two seriesconnected switches, one of which is said to be a high channel switch,and the other, a low channel switch, and which are each provided with arecovery diode in parallel, each of said pairs having a middle pointwhich constitutes an AC output terminal which can be connected to aphase impedance of the motor, the said inverter having output voltagesbetween the output terminals; iii. a device for controlling the switchesbeing connected thereto for applying thereto modulated pulses forensuring closing and opening thereof according to a modulation; iv. ameans for reading the DC current in one of the said conductors and fordelivering an image signal of this DC current; v. a processing meansconnected to the reading means, said processing means comprising meansfor detecting an instability of the image signal and means forgenerating a stabilization control signal when the said instability isdetected; vi. a means for reducing the output voltages of the inverter,said means being connected to the processing means so as to receive thestabilization control signal, and comprising means for modifying themodulated pulses delivered by the control device when the stabilizationcontrol signal is emitted, wherein the said conductors conduct a reversecurrent passing through the said recovery diodes and the processingmeans deliver a reverse current excess signal (ST) and include aprocessing circuit connected to the current reading means and providinga filtered peak signal representative of the peak value of the reversecurrent and a comparator comparing this signal (I_(d)) with anadjustable reference value (I_(REF)) for generating when I_(d) >I_(REF),the reverse current excess signal (ST) applicable to the output voltagereduction means.
 2. Frequency converter according to claim 1, wherein adelay element is provided for maintaining the reverse current excesssignal (ST) for a given time.
 3. Frequency converter according to claim1, which comprises an integrating means for providing the mean value(I_(d)) of the reverse current and comparing this means value with agiven threshold, one input of said integrating means being connected tothe current reading means, whereas an output of said integrating meansdelivers a signal (G) inhibiting the reverse current excess signal (ST)when the motor operates as a generator.
 4. Frequency converter accordingto claim 1, characterized by the fact that a comparator (32) isconnected to the current reading means (21) and is adapted for comparingan image signal of the motor current (I_(t)) with a reference value soas to deliver a motor current excess signal (ST'), the reverse currentexcess (ST) and motor current excess (ST') signals being applied to theinputs of an OR gate (33) whose output is connected via a delay element(34) to the inverter.
 5. A frequency converter for an AC power supply ofan asynchronous type motor, comprising:i. a rectifier bridge havinginput AC terminals which can be connected to a multiphase network andtwo DC output terminals connected to two respective conductors of a DCintermediate circuit; ii. an inverter having two DC input terminalsrespectively connected to the said conductors so as to receive a DCcurrent provided by the rectifier and flowing in the conductors, saidinverter comprising three pairs of static switches; each pair beingconnected to the two DC input terminals and comprising two seriesconnected switches, one of which is said to be a high channel switch,and the other, a low channel switch, and which are each provided with arecovery diode in parallel, each of said pairs having a middle pointwhich constitutes an AC output terminal which can be connected to aphase impedance of the motor, the said inverter having output voltagesbetween the output terminals; iii. a device for controlling the switchesbeing connected thereto for applying thereto modulated pulses forensuring closing and opening thereof according to a modulation; iv. ameans for reading the DC current in one of the said conductors and fordelivering an image signal of this DC current; v. a processing meansconnected to the reading means, said processing means comprising meansfor detecting an instability of the image signal and means forgenerating a stabilization control signal when the said instability isdetected; vi. a means for reducing the output voltages of the inverter,said means being connected to the processing means so as to receive thestabilization control signal, and comprising means for modifying themodulated pulses delivered by the control device when the stabilizationcontrol signal is emitted, wherein: the processing means comprises ameans establishing the means value (I_(m)) of the image signal (I) ofthe current in the intermediate circuit, as well as an A-D converterreceiving a mean value signal (I_(m)) and delivering a digital signal(I_(mn)), the voltage reduction means include a processor having meansfor sampling the digital signal (I_(mn)) and means for evaluating theamplitude and/or the frequency of oscillation of the signal (I_(mn)),the control device comprises modulation control means for modulating theclosing of the switches (T1-T6), the evaluation means acting on themodulation control means for correcting said modulation as a function ofthe oscillation of the mean current in the intermediate circuit. 6.Frequency converter according to claim 5, characterized by the fact thatthe voltage reduction means (25) and the control device (20) areimplemented in a microprocessor.
 7. A frequency converter for an ACpower supply of an asynchronous type motor, comprising:i. a rectifierbridge having input AC terminals which can be connected to a multiphasenetwork and two AC output terminals connected to two respectiveconductors of a DC intermediate circuit; ii. an inverter having two DCinput terminals respectively connected to the said conductors so as toreceive a DC current provided by the rectifier and flowing in theconductors, said inverter comprising three pairs of static switches,each pair being connected to the two DC input terminals and comprisingtwo series connected switches, one of which is said to be a high channelswitch, and the other, a low channel switch, and which are each providedwith a recovery diode in parallel, each of said pair shaving a middlepoint which constitutes an AC output terminal which can be connected toa phase impedance of the motor, the said inverter having output voltagesbetween the output terminals; iii. a device for controlling the switchesbeing connected thereto for applying thereto modulated pulses forensuring closing and opening thereof according to a modulation; iv. ameans for reading the DC current in one of the said conductors and fordelivering an image signal of this DC current; v. a processing meansconnected to the reading means, said processing means comprising meansfor detecting an instability of the image signal and means forgenerating a stabilization control signal when the instability isdetected; vi. a means for reducing the output voltages of the inverter,said means being connected to the processing means so as to receive thestabilization control signal, and comprising means for alternativedisabling the high channel switches and the low channel switchessynchronously with the said modulation when the stabilization controlsignal is emitted.
 8. A frequency converter for an AC power supply of anasynchronous type motor, comprising:i. a rectifier bridge having inputAC terminals which can be connected to a multiphase network and two DCoutput terminals connected to two respective conductors of a DCintermediate circuit; ii. an inverter having two DC input terminalsrespectively connected to the said conductors so as to receive a DCcurrent provided by the rectifier and flowing in the conductors, saidinverter comprising three pairs of static switches, each pair beingconnected to the two DC input terminals and comprising two seriesconnected switches, one of which is said to be a high channel switch,and the other, a low channel switch, and which are each provided with arecovery diode in parallel, each of said pairs having a middle pointwhich constitutes an AC output terminal which can be connected to aphase impedance of the motor, the said inverter having output voltagesbetween the output terminals; iii. a device for controlling the switchesbeing connected thereto for applying thereto modulated pulses forensuring closing and opening thereof according to a modulation; iv. ameans for reading the DC current in one of the said conductors and fordelivering an image signal of this DC current; v. a processing meansconnected to the reading means, said processing means comprising meansfor detecting an instability of the image signal and means forgenerating a stabilization control signal when the said instability isdetected; vi. a means for reducing the output voltages of the inverter,said means being connected to the processing means so as to receive thestabilization control signal, and comprising means for only disablingthe high channel switches or the low channel switches when thestabilization control signal is emitted.